Minimum-spacing circuit design and layout for pica

A method for testing the resolution of an imaging device, comprising:

• forming a plurality of field effect transistors (FETs) having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by distance governed by a minimum feature size of a fabrication technology;
• forming two NOR gates, each of which accepts the input signal and a respective select signal, to control the FETs;
• activating the FETs by providing an input signal;
• suppressing light emissions from one or more of the activated FETs by providing one or more select signals to the NOR gates;
• and
• changing the select signals to the NOR gates to suppress light emissions from different FETs devices.

A method for testing the resolution of an imaging device, comprising:

• forming a plurality of pairs of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by distance governed by a target resolution size;
• forming first logic circuits configured to control pairs of the semiconductor devices;
• forming second logic circuits configured to accept outputs of the respective pairs of semiconductor devices and to reproduce the input signal, wherein the output of each second logic circuit is connected as the input signal to a subsequent pair of semiconductor devices;
• activating the semiconductor devices by providing an input signal;
• and
• suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.