Back to results
US 2013/0279285 A1Published application
Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHan Sik Yoo, Bum Jae Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory cell array region and a column decoder. The memory cell array region includes a plurality of memory cell arrays that are arranged in row and column directions. The column decoder includes a first column select line (CSL) driver and a second CSL driver that are disposed adjacent to a first edge of the memory cell array region extending in the row direction and that have different physical layouts.
Claims20
A semiconductor memory device comprising:
- a memory cell array region comprising a plurality of memory cell arrays each array including memory cells that are arranged in row and column directions, sub-wordline drivers that are disposed between memory cell arrays in the row direction, and conjunction regions that are disposed between sub-wordline drivers in the column direction;
- protrusion conjunction regions that are disposed adjacent to a first group of the sub-wordline drivers positioned at a first edge of the memory cell array region extending in the row direction and that protrude from the first edge in the column direction;
- and
- a column decoder comprising first column select line (CSL) drivers each having a first physical layout and second CSL drivers each having a second physical layout different from the first physical layout, the first and second CSL drivers being disposed adjacent to the first edge of the memory cell array region,
- wherein the number of the first CSL drivers is greater than the number of the second CSL drivers.
2 more elements
A semiconductor memory device comprising:
- a memory cell array region comprising a plurality of memory cell arrays arranged in row and column directions;
- a protrusion portion protruding from at least one edge of the memory cell array region in at least one of the row and column directions;
- sub-wordline drivers disposed between memory cell arrays in the row direction, and configured to generate word line signals in response to driver signals;
- a row decoder including first drivers and second drivers, the row decoder disposed adjacent to a first edge of the memory cell array region extending in the column direction, and configured to generate the driver signals;
- and
- a column decoder including third drivers and fourth drivers, the column decoder disposed adjacent to a second edge perpendicular to the first edge of the memory cell array region extending in the row direction, and configured to generate column select line (CSL) signals,
- wherein at least one of the first drivers includes a physical layout different from at least one of the second drivers, or at least one of the third drivers includes a physical layout different from at least one of the fourth drivers.
4 more elements
A semiconductor memory device comprising:
- a memory cell array region including a plurality of memory cell arrays arranged in row and column directions;
- a column decoder including a plurality of column select line (CSL) drivers disposed adjacent to a first edge of the memory cell array region extending in the row direction, and configured to generate a plurality of column select line signals;
- and
- a row decoder including a plurality of main word line (MWL) drivers disposed adjacent to a second edge of the memory cell array region extending in the column direction, and configured to generate a plurality of main word line signals,
- wherein the CSL drivers includes first and second CSL drivers, each of the first CSL drivers including a physical layout different from each of the second CSL drivers, and
- wherein a number of the first CSL drivers is greater than a number of the second CSL drivers.
3 more elements
Dependencies are inferred from the claim text.