US 2013/0279282 A1 · E-FUSE ARRAY CIRCUIT

Abstract

An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor.

Claims14

Dependent claims

An e-fuse array circuit comprising:

a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line;
a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor;
a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line;
and
a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor.

2 more elements

An use array circuit comprising:

a plurality of e-fuse cells disposed in a form of M by N matrix, and divided into N groups extended toward an Y direction, each group comprising M e-fuse cells,
wherein each of the e-fuse cells comprises a select transistor and an e-fuse transistor, and the select transistors of the e-fuse cells in the same group has a gate terminal coupled to a corresponding select line and a source/drain path between a respective bit line and a respective e-fuse transistor while all of the e-fuse transistors in the same group have a gate terminal coupled to a common program/read line.

Dependencies are inferred from the claim text.

E-fuse array circuit

Life of this patent

E-fuse array circuit

Life of this patent

Abstract

Claims14