Separate microchannel voltage domains in stacked memory architecture
AssigneeIntel Corporation
InventorAndre Schaefer
Life of this patent
Estimating the term…
Abstract
Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.
Claims26
A memory device comprising:
- a memory stack including one or more coupled memory dies, wherein the memory stack includes a plurality of microchannels;
- and
- a logic chip coupled with the memory stack, the logic chip including a memory controller;
- wherein each of the plurality of microchannels includes a separate voltage domain;
- and
- wherein a voltage level is controlled separately for each of the plurality of microchannels.
A method comprising:
- tracking traffic for a first microchannel of a memory device, the memory device including a logic chip coupled with a memory stack of one or more coupled memory dies, the memory device including a plurality of microchannels, each microchannel having a voltage domain;
- detecting a traffic pattern for the first microchannel;
- determining an advantage relating to a change in a voltage of the microchannel;
- and
- requesting a change of the voltage of the microchannel.
14-15. (canceled)
A system comprising:
- a processor to process data of the system;
- a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both;
- and
- a memory to store data, the memory including a stacked memory device, the stacked memory device including:
- a memory stack including one or more coupled memory dies, wherein the memory stack includes a plurality of microchannels;
- and
- a logic chip coupled with the memory stack, the logic chip including a memory controller;
- wherein each of the plurality of microchannels includes a separate voltage domain;
- and
- wherein a voltage level is controlled separately for each of the plurality of microchannels.
A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
- tracking traffic for a first microchannel of a memory device, the memory device including a logic chip coupled with a memory stack of one or more coupled memory dies, the memory device including a plurality of microchannels, each microchannel having a voltage domain;
- detecting a traffic pattern for the first microchannel;
- determining an advantage relating to a change in a voltage of the microchannel;
- and
- requesting a change of the voltage of the microchannel.
Dependencies are inferred from the claim text.