Back to results
US 2013/0279274 A1Published application
Semiconductor apparatus
AssigneeSK hynix Inc.
InventorHong Gyeom KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.
Claims23
A semiconductor apparatus comprising:
- a memory cell block configured to store data;
- a fuse block comprising a plurality of fuses configured to store fuse information;
- an I/O driver configured to output the data transmitted through a global line to a pad;
- and
- a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.
2 more elements
A semiconductor apparatus comprising:
- a decoder configured to decode an inputted address to generate a fuse select signal, when a read command is applied during a test mode;
- a fuse block comprising a plurality of fuses and configured to output fuse information of a fuse selected according to the fuse select signal, where the fuse information is transmitted via a test global line;
- a fuse driver configured to output the fuse information transmitted through the test global line to a pad during the test mode.
A semiconductor apparatus comprising:
- a master chip and a plurality of slave chips, which are electrically connected and stacked,
- wherein each of the slave chips comprises a memory cell block configured to store data, and
- the master chip comprises:
- a fuse block comprising a plurality of fuses configured to store fuse information;
- an I/O driver configured to output the data transmitted through a global line to a pad;
- and
- a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.
4 more elements
A semiconductor apparatus comprising:
- a master chip and a plurality of slave chips, which are electrically connected through a through-chip via and stacked,
- wherein each of the slave chips comprises a memory cell block configured to store data, and
- the master chip comprises:
- a decoder configured to decode an inputted address to generate a fuse select signal, when a read command is applied during a test mode;
- a fuse block comprising a plurality of fuses and configured to output fuse information of a fuse selected according to the fuse select signal;
- an I/O driver configured to output the data transmitted through a global line to a pad during a normal operation mode;
- and
- a fuse driver configured to output the fuse information transmitted through a test global line to the pad during the test mode.
5 more elements
Dependencies are inferred from the claim text.