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US 2013/0279272 A1Published application
Semiconductor device having fuse circuit
AssigneeSK hynix Inc.
InventorKwi-Dong KIM
Life of this patent
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Abstract
A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.
Claims10
A semiconductor device comprising:
- a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal;
- and
- a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.
A semiconductor device comprising:
- a first cell mat configured to be inactive in response to a first cell mat selection signal;
- a second cell mat configured to be inactive in response to a second cell mat selection signal;
- a pulse generation circuit configured to activate an enable pulse signal in response to an active command and deactivate the enable pulse signal in response to a column command;
- at least one fuse circuit configured to store a first repair address for a column repair of the first cell mat and a second repair address for a column repair of the second cell mat, and output the first repair address or the second repair address in response to the enable pulse signal;
- and
- a column repair circuit configured to perform a column repair operation using the first repair address or the second repair address which is output from the at least one fuse circuit.
3 more elements
The semiconductor device of claim wherein the at least one fuse circuit comprises
- a first fuse configured to store one bit of the first repair address;
- a second fuse configured to one bit of the second repair address;
- a transfer unit configured to transfer the first repair address having one bit, which is stored in the first fuse, to an output node in response to the enable pulse signal when the first cell mat selection signal is activated, or the second repair address having one bit, which is stored in the second fuse, to the output node in response to the enable pulse signal when the second cell mat selection signal is activated;
- and
- a latch unit configured to latch the first repair address having one bit or the second repair address having one bit, which is transferred to the output node.
2 more elements
The semiconductor device of claim wherein the at least one fuse circuit comprises
- a pre-charge unit configured to connect a first node to a first voltage supply terminal in response to a pre-charge signal and pre-charge the first node to a first voltage level;
- a first fuse unit configured to have a first fuse and connect a second node to a first voltage supply terminal according to a cutting state of the first fuse when the first cell mat selection signal is activated;
- a second fuse unit configured to have a second fuse and connect the second node to a second voltage supply terminal according to a cutting state of the second fuse when the second cell mat selection signal is activated;
- a transfer unit configured to connect the first node to the second node in response to the enable pulse signal;
- and
- a latch unit configured to latch a voltage level of the first node.
3 more elements
Dependencies are inferred from the claim text.