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US 2013/0279271 A1Published application
Pipe register circuit and semiconductor memory apparatus having the same
AssigneeSK hynix Inc.
InventorHyun Su YOON
Life of this patent
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Abstract
A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.
Claims16
A pipe register circuit comprising:
- an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals;
- and
- an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.
A semiconductor memory apparatus comprising:
- a cell array including a plurality of memory cells arranged in order to store data;
- a pipe register configured to receive and temporarily store address signals input from an external, generate an address output control signal for controlling output of the address signals, and output data stored in the cell array by the generated address output control signal;
- and
- an output driver configured to output data, which is output by the address signals, to an external.
1 more element
Dependencies are inferred from the claim text.