Nonvolatile memory device, system and programming method with dynamic verification mode selection

A nonvolatile memory device, comprising:

• a memory cell array including a plurality of memory cells connected to word lines and bit lines;
• a voltage generator configured to generate a program voltage and verify voltages;
• an address decoder configured to apply the program voltage in a programming operation to a selected word line among the word lines in response to an address and the verify voltages to the selected word line in a verifying operation;
• a plurality of page buffers connected to the bit lines and configured to store data to be programmed to memory cells connected to the selected word line in the programming operation and to store data read from the memory cells in the verifying operation;
• and
• a control logic configured to control the voltage generator, the address decoder and the plurality of page buffers to proceed a plurality of program loops having the programming operation and the verifying operation,
• wherein the control logic proceeds the verifying operation using 2-step verification mode when a number of the program loops is not over a predetermined value and the verifying operation using 1-step verification mode when the number of the program loops is over the predetermined value.

A programming method of a nonvolatile memory device, comprising:

• generating a program pulse;
• applying the program pulse in a program loop;
• generating verification pulses according to 2-step verification mode when a number of the program loop is not over a pre-determined value or verification pulses according to 1-step verification mode when the number of the program loop is over the pre-determined value;
• and
• applying the verification pulses in the program loop.

A memory system comprising:

• a plurality of nonvolatile memory devices;
• and
• a controller configured to control the plurality of nonvolatile memory devices,
• wherein each of the plurality of nonvolatile memory devices comprises, a memory cell array including a plurality of memory cells connected to word lines and bit lines;
• a voltage generator configured to generate a program voltage and verify voltages;
• an address decoder configured to the program voltage in a programming operation to selected word line among the word lines in response to an address and the verify voltages to the selected word line in a verifying operation;
• a plurality of page buffers connected to the bit lines and configured to store data to be programmed to memory cells in the programming operation and to store data read from the memory cells in the verifying operation;
• and
• a control logic configured to control the voltage generator, the address decoder and the plurality of page buffers to proceed a plurality of program loops having the programming operation and the verifying operation,
• wherein the control logic proceeds the verifying operation using 2-step verification mode when a number of the program loops is not over a predetermined value and the verifying operation using 1-step verification mode when the number of the program loops is over the predetermined value.