Semiconductor memory device and method for controlling the same

A reading method of semiconductor memory device, the method comprising:

• transferring a first voltage to a bit line by a first transistor having a first current driving force;
• transferring a second voltage to a detector by a second transistor, while the first transistor transfers the first voltage through the bit line, the second voltage being generated by a source different from a source of the first voltage, the detector receiving the second voltage to detect a current flowing through the bit line;
• and
• connecting the detector and the bit line and then transferring read data to a latch circuit depending on the potential of the detector.

A semiconductor memory device comprising:

• a memory cell array comprising a first block and a second block, the first block and the second block each including the plurality of NAND strings each comprising the plurality of memory cells formed on a well and connected in series;
• a source line driver setting the well to a ground potential and comprising a first node, the source line driver charging and discharging potentials of the sources of the first block and the second block via the first node;
• and
• a voltage controller configured to supply a voltage to the fifth node and turn on the transistor to control charge and discharge of the first node,
• wherein the voltage controller includes:
• a voltage booster boosting, during a read operation, a potential of the first node, and upon detecting when the potential of the source of the second block exceeds a predetermined value, stopping boosting the potential of the first node;
• and
• a pull-down driver detecting the potential of the source and to controllably discharge the potential of the first node when the potential of the source exceeds a second predetermined value.