Semiconductor memory storage apparatus having charge storage layer and control gate

An operation method of a semiconductor memory storage apparatus including a memory cell array comprising:

• reading data from a memory cell in the memory cell array, and storing the data in a first latch;
• storing an expected value to the second latch, the expected value being stored a first area in the memory array and being a value expected to be read from the memory cell;
• transferring first data obtained by inverting the expected value to a detector via a first node, thereafter transferring second data obtained by inverting the data to the detector via the second node, and setting a value of the detector to third data;
• transferring a value corresponded to the third data to a third latch via the first node;
• and
• setting a value of the detector to fourth data, thereafter transferring the expected value to detector via the first node, by transferring the expected value to the first node and transferring a value corresponding to a potential level of the first node to the detector.

An operation method of semiconductor memory storage apparatus including a memory cell array comprising:

• reading data from a memory cell in a memory cell array, and storing the read data in a first latch via a first node;
• transferring an expected value being expected to be read from the memory cell, to the first node from a second latch in which the expected value is stored;
• evacuating the read data stored in the first latch to an evacuation circuit;
• performing a first operation by transferring the expected value stored in the first node to the first latch;
• and
• performing a second operation by transferring the read data evacuated to the evacuation circuit to the first node holding the expected value.