Multi-level interconnect apparatus

A multi-level interconnect apparatus, comprising:

• a multi-chip module (MCM) substrate including a substrate body having a first side and a second side opposite the first side;
• a processing unit disposed on the second side of the substrate body;
• a first input/output (I/O) unit disposed on the first side of the substrate body and configured to be electrically communicable with the processing unit along a first dimension defined through the substrate body;
• and
• a second I/O unit disposed on the second side of the substrate body and configured to be electrically communicable with the processing unit along a second dimension defined along the second side of the substrate body.

A multi-level interconnect apparatus, comprising:

• a multi-chip module (MCM) substrate including a substrate body having a first side and a second side opposite the first side;
• a processing unit, including a plurality of processors, disposed on a central portion of the second side of the substrate body;
• a first input/output (I/O) unit disposed on the first side of the substrate body and configured to be electrically communicable with the plurality of processors of the processing unit along a thickness dimension of the substrate body;
• and
• a second I/O unit disposed on a periphery of the second side of the substrate body and configured to be electrically communicable with the plurality of processors of the processing unit along a planar dimension of the substrate body.