Method and Apparatus for Controlling Writing of Data to Graphic Memory

An apparatus for controlling an operation of writing data including a plurality of consecutive input data to a graphic memory, comprising:

• a controller configured to control the plurality of consecutive input data including first input data, second input data, third input data and fourth input data;
• and
• a plurality of memory areas including a first memory area and a second memory area, the plurality of memory areas forming the graphic memory, the first memory area being separate from the second memory area,
• wherein the first input data is written to the first memory area and simultaneously the second input data is written to the second memory area, and
• the third input data is written to the first memory area and simultaneously the fourth input data is written to the second memory area.

A method of controlling an operation of writing data including a plurality of consecutive input data to a graphic memory having a first memory area and a second memory area, the first memory area being separate from the second memory area, the plurality of consecutive input data including first input data, second input data, third input data and fourth input data, the method comprising:

• receiving the first input data;
• latching the first input data in response to a first pulse of a first clock signal;
• receiving the second input data;
• writing simultaneously the first input data to the first memory area in response to a second clock signal and the second input data to the second memory area in response to a third clock signal;
• receiving the third input data;
• latching the third input data in response to a second pulse of the first clock signal;
• receiving the fourth input data;
• and
• writing simultaneously the third input data to the first memory area in response to the second clock signal and the fourth input data to the second memory area in response to the third clock signal.

An apparatus for controlling an operation of writing data including a plurality of data streams to a graphic memory, comprising:

• a controller configured to control the plurality of data streams comprising a first data stream and a second data stream, each of the plurality of data streams comprising a plurality of consecutive input data with odd input data and even input data, the odd input data including a first input data, the even input data including a second input data;
• and
• a plurality of memory areas including a first memory area and a second memory area, the plurality of memory areas forming the graphic memory, the first memory area being separate from the second memory area, the first memory area having an upper sub-block and a lower sub-block, the second memory area having an upper sub-block and a lower sub-block,
• wherein the odd input data of the first data stream is written to one of the first memory area and the second memory area, and the even input data of the first data stream is written to the other of the first memory area and the second memory area, and
• the odd input data of the second data stream is written to one of the first memory area and the second memory area, and the even input data of the second data stream is written to the other of the first memory area and the second memory area.