Embedded displayport system and method for controlling panel self refresh mode

An eDP system comprising a timing controller configured to recover a stream clock,

• wherein the timing controller comprises:
• an oscillator configured to provide an oscillator clock;
• a stream data regeneration block configured to output a link symbol clock and first and second stream data, transmitted from a source device, as a reference clock and first and second regenerated stream data in a general mode, store a number, obtained by counting the oscillator clock while the link symbol clock is counted by a number corresponding to the first stream data, as first stored stream data, store a number, obtained by counting the stream clock during one period of a divided clock obtained by dividing the oscillator clock by the first stored stream data, as second stored stream data, and output the oscillator clock and the first and second stored stream data as the reference clock and the first and second regenerated stream data according to a panel mode signal in a PSR mode;
• and
• a stream clock recovery block configured to recover the stream clock using the reference clock and the first and second regenerated stream data.

An eDP system comprising a timing controller configured to generate a reference clock for recovering a stream clock,

• wherein the timing controller comprises:
• an oscillator configured to provide an oscillator clock;
• a first stored stream data generator configured to generate first stored stream data based on a number obtained by counting the oscillator clock while a link symbol clock transmitted from a source device is counted by a number corresponding to first stream data transmitted from the source device;
• a divider configured to divide the oscillator clock by the first stored stream data;
• a second stored stream data generator configured to generate second stored stream data based on a number obtained by counting a currently-output stream clock during one period of a divided clock outputted from the divider;
• a stream data buffer configured to store the first and second stored stream data and provide the second stored stream data to the divider;
• and
• a selection circuit configured to select and output the link symbol clock and the first and second stream data as the reference clock and first and second regenerated stream data in a general mode and select and output the oscillator clock and the first and second stored stream data stored in the stream data buffer as the reference clock and the first and second regenerated stream data in response to a panel mode signal in a PSR mode.

A method for controlling a PSR mode of an eDP system, comprising:

• storing a number, obtained by counting an oscillator clock provided from an oscillator while a link symbol clock is counted by a number corresponding to first stream data having a fixed value, as first stored stream data in a general mode;
• storing a number, obtained by counting a stream clock during one period of a divided clock obtained by dividing the oscillator clock by the first stored stream data, as second stored stream data in the general mode;
• and
• selecting the oscillator clock and the first and second stored stream data and providing the selected clock and data as a reference clock and first and second regenerated stream data for recovering a stream clock in a PSR mode.