Bus-line arrangement in a gate driver

A circuit (30) comprising:

• a bus area (35) comprising M bus lines configured to receive a plurality of clock signals, M being a positive integer greater than 3;
• and
• a plurality of signal lines arranged to separately convey the clock signals received from the M bus lines, said plurality of signal lines comprising a plurality of adjacent signal-line pairs, each signal-line pair having a resistance difference, said signal lines comprising a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

A display panel, comprising:

• a display area comprising an array of pixels;
• a gate driver configured to provide a plurality of sequential gate signals to the display area for controlling the array of pixels in a frame time;
• a bus area comprising M bus lines configured to receive a plurality of clock signals, M being a positive integer greater than 3, and a plurality of signal lines arranged to separately provide the clock signals from the M bus lines to the gate driver, wherein the plurality of sequential gate signals are provided in response to the clock signals, said plurality of signal lines comprising a plurality of adjacent signal-line pairs, each signal-line pair having a resistance difference, said signal lines comprising a maximum resistance value and a minimum resistance value, and wherein the bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.