Differential signal correction circuit

A differential signal correction circuit, comprising:

• a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, and a source of the first transistor is grounded;
• a second transistor, wherein a source of the second transistor is coupled with the gate of the first transistor, and a gate of the second transistor is coupled with a drain of the first transistor;
• a third transistor, wherein a source of the third transistor is configured to receive a second input signal, the first input signal and the second input signal are differential signal pair, a drain of the third transistor is coupled with the drain of the first transistor, and a gate of the third transistor is coupled with a drain of the second transistor;
• a fourth transistor, wherein a gate of the fourth transistor is coupled with the source of the third transistor, a drain of the fourth transistor is coupled with the gate of the third transistor, and a source of the fourth transistor is grounded;
• a first load coupled between the drain of the first transistor and a first power source;
• and
• a second load coupled between the drain of the fourth transistor and a second power source;
• wherein the first input signal and the second input signal are phase corrected by the first transistor, the second transistor, the third transistor and the fourth transistor, a first output current signal is collected from a coupled node of the drain of the first transistor and the gate of the second transistor, a second output current signal is collected from a coupled node of the gate of the third transistor and the drain of the fourth transistor, the first output current signal is converted into a first output voltage signal by the first load, the second output current signal is converted into a second output voltage signal by the second load, the first output voltage signal is fed back to the first transistor and the second transistor via the coupled node of the drain of the first transistor and the gate of the second transistor, the second output voltage signal is fed back to the third transistor and the fourth transistor via the coupled node of the gate of the third transistor and the drain of the fourth transistor for gain and secondary phase correction.