US 2013/0278309 A1 · SEMICONDUCTOR WAFER AND METHOD FOR AUTO-CALIBRATING INTEGRATED CIRCUIT CHIPS USING PLL AT WAFER LEVEL

Abstract

In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

Claims6

Dependent claims

A method of auto-calibrating integrated circuit chips at a wafer level by calibrating an operation frequency of the integrated circuit chips, the method comprising:

supplying DC power to the integrated circuit chips;
selecting an integrated circuit chip to perform calibration of an operation frequency;
receiving an operation frequency that is generated in the selected to integrated circuit chip;
calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency;
generating a frequency calibration value of the operation frequency using the phase difference;
transmitting a control signal comprising the frequency calibration value to the integrated circuit chip;
and
releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

5 more elements

A semiconductor wafer for auto-calibrating an operation frequency of integrated circuit chips, the semiconductor wafer comprising:

an integrated circuit chip area;
a probe area in which a calibration controller of an operation frequency is connected to the outside of the semiconductor wafer, wherein the calibration controller includes a phase-locked loop that calculates a phase difference by comparing a phase of a calibration target frequency and a phase of the operation frequency, and generates an operation frequency calibration value using the phase difference;
a signal transmitting area that is connected to the probe area to transmit a signal of the integrated circuit chips to the calibration controller;
and
a buffer that relays a signal that is exchanged between the integrated circuit chips and the signal transmitting area.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor wafer and method for auto-calibrating integrated circuit chips using pll at wafer level

Life of this patent

Semiconductor wafer and method for auto-calibrating integrated circuit chips using pll at wafer level

Life of this patent

Abstract

Claims6