Semiconductor device having calibration circuit that adjusts impedance of output buffer

A semiconductor device comprising:

• a data terminal;
• first and second power supply lines;
• a first output unit connected between the first power supply line and the data terminal, an impedance of the first output unit being controlled based on a first control code;
• a second output unit connected between the second power supply line and the data terminal, an impedance of the second output unit being controlled based on a second control code;
• a first code generation unit including a first impedance adjustment unit and a first reference transistor connected in series between the first power supply line and the second power supply line, an impedance of the first impedance adjustment unit being controlled based on the first control code, the first impedance adjustment unit generating the first control code such that a potential of a connection point between the first impedance adjustment unit and the first reference transistor matches a reference potential;
• and
• a second code generation unit including a second impedance adjustment unit and a second reference transistor connected in series between the first power supply line and the second power supply line, an impedance of the second impedance adjustment unit being controlled based on the second control code, the second impedance adjustment unit generating the second control code such that a potential of a connection point between the second impedance adjustment unit and the second reference transistor matches the reference potential.

A system comprising:

• a substrate;
• a calibration resistor on the substrate;
• and
• a semiconductor chip on the substrate, the semiconductor chip comprising:
• a calibration terminal coupled to the calibration resistor;
• a data terminal;
• an output buffer coupled to the data terminal, the output buffer including a plurality of first transistors and a plurality of second transistors, the first and second transistors being different in conductivity type from each other, an impedance of the first transistors being controlled in response to first calibration information, an impedance of the second transistors being controlled in response to second calibration information;
• and
• a calibration circuit coupled to the calibration terminal, being configured to compare a reference voltage with a first voltage of the calibration terminal to generate a first bias voltage, to compare the reference voltage with a second voltage responsive to the first bias voltage to generate a second bias voltage, to generate the first calibration information in response to the first bias voltage, and to generate the second calibration information in response to the second bias voltage.