Minimum-spacing circuit design and layout for pica

A circuit, comprising:

• a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
• a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal;
• and
• a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
• wherein one of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.

A test circuit, comprising:

• a plurality of test cells arranged in a line, each test cell comprising:
• a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
• a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal provided by the output of a previous test cell;
• and
• a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
• wherein one of said NOR gates in each test cell biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.