Voids in STI Regions for Forming Bulk FinFETs

An integrated circuit structure comprising:

• a first semiconductor strip over a semiconductor substrate;
• a second semiconductor strip over the semiconductor substrate;
• a first shallow-trench isolation (STI) region over the substrate and between and adjoining the first semiconductor strip and the second semiconductor strip, wherein the first STI region comprises a void therein, and wherein a portion of the first semiconductor strip over a top surface of the first STI region forms a first fin, and a portion of the second semiconductor strip over the top surface of the first STI region forms a second fin;
• a second STI region over the substrate, wherein the second STI region does not comprise any void;
• a gate dielectric over top surfaces and sidewalls of the first fin and the second fin;
• and
• a gate electrode over the gate dielectric, wherein the gate electrode is directly over the void, the first fin, and the second fin.

An integrated circuit structure comprising:

• a first plurality of fins over a substrate, the first plurality of fins being spaced apart from one another by respective first isolation regions each having a first width, the first isolation regions comprising voids;
• a second plurality of fins over a substrate;
• a second isolation region laterally between the first plurality of fins and the second plurality of fins, the second isolation region having a second width, the second width being greater than the first width, the second isolation region having a top surface higher than the top surfaces of the first isolation regions;
• a gate dielectric over at least one of the first plurality of fins;
• and
• a gate electrode over the gate dielectric.