Interface-free metal gate stack
AssigneeInternational Business Machines Corporation
InventorsTakashi ANDO, Kisik CHOI, Matthew W. COPEL, Richard A. HAIGHT
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Abstract
A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
Claims10
A transistor formed by a process comprising:
- forming a metal layer on a high dielectric constant layer formed on a semiconductor layer;
- forming a silicon containing layer over the metal layer, wherein a silicon dioxide layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer;
- forming a first gate stack for a pFET region, wherein the first gate stack comprises a first portion of the metal layer and a first portion of the silicon containing layer, and wherein a first portion of the silicon dioxide layer resides on the first portion of the metal layer;
- forming a second gate stack for an nFET region, wherein the second gate stack comprises a second portion of the metal layer and a second portion of the silicon containing layer, and wherein a second portion of the silicon dioxide layer resides on the second portion of the metal layer;
- selectively removing the first portion of the silicon containing layer;
- and
- thereafter, removing the first portion of the silicon dioxide layer residing on the first portion of the metal layer while maintaining the second portion of the silicon dioxide layer on the second portion of the metal layer.
A gate stack for a transistor formed by a process comprising:
- forming a metal layer on a high dielectric constant layer formed on a semiconductor layer;
- forming a silicon containing layer over the metal layer, wherein a silicon dioxide layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer;
- forming a first gate stack for a pFET region, wherein the first gate stack comprises a first portion of the metal layer and a first portion of the silicon containing layer, and wherein a first portion of the silicon dioxide layer resides on the first portion of the metal layer;
- forming a second gate stack for an nFET region, wherein the second gate stack comprises a second portion of the metal layer and a second portion of the silicon containing layer, and wherein a second portion of the silicon dioxide layer resides on the second portion of the metal layer;
- selectively removing the first and second portions of the silicon containing layer;
- and
- thereafter, contemporaneously removing the first and second portions of the silicon dioxide layer residing on the first and second portions of the metal layer, respectively.
Dependencies are inferred from the claim text.