Ldmos device with field effect structure to control breakdown voltage, and methods of making such a device

An LDMOS device, comprising:

• a source region and a drain region formed in a semiconducting substrate;
• a gate electrode positioned above said substrate, said gate electrode being generally laterally positioned between said source region and said drain region;
• a metal-1 field plate positioned above said gate electrode in a layer of insulating material that is formed above said substrate;
• a silicide block layer formed above said substrate, said silicide block layer being positioned in an area between said gate electrode and said drain region;
• at least one source contact that is conductively coupled to said metal-1 field plate;
• and
• a plurality of individual conductive contacts that are conductively coupled to said metal-1 field plate, wherein at least some of said plurality of individual conductive contacts extend downward toward said substrate and land on said silicide block layer in said area between said gate electrode and said drain region.

An LDMOS device, comprising:

• a source region and a drain region formed in a semiconducting substrate;
• a gate electrode positioned above said substrate, said gate electrode being generally laterally positioned between said source region and said drain region;
• a metal-1 field plate positioned above said gate electrode in a layer of insulating material that is formed above said substrate;
• a silicide block layer formed above said substrate, said silicide block layer being positioned in an area between said gate electrode and said drain region;
• at least one source contact that is conductively coupled to said metal-1 field plate;
• and
• a plurality of line-type features that are conductively coupled to said metal-1 field plate, wherein at least one of said plurality of line-type features extends downward toward said substrate and lands on said silicide block layer in said area between said gate electrode and said drain region.

An LDMOS device, comprising:

• a source region and a drain region formed in a semiconducting substrate;
• a gate electrode positioned above said substrate, said gate electrode being generally laterally positioned between said source region and said drain region;
• a metal-1 field plate positioned above said gate electrode in a layer of insulating material that is formed above said substrate;
• a silicide block layer formed above said substrate, said silicide block layer being positioned in an area between said gate electrode and said drain region;
• at least one source contact that is conductively coupled to said metal-1 field plate;
• and
• a plurality of ring-type features that are conductively coupled to said metal-1 field plate, wherein at least a portion of at least one of said plurality of ring-type features extends downward toward said substrate and lands on said silicide block layer in said area between said gate electrode and said drain region.

An LDMOS device, comprising:

• a source region and a drain region formed in a semiconducting substrate;
• a gate electrode positioned above said substrate, said gate electrode being generally laterally positioned between said source region and said drain region;
• a metal-1 field plate positioned above said gate electrode in a layer of insulating material that is formed above said substrate;
• a silicide block layer formed above said substrate, said silicide block layer being positioned in an area between said gate electrode and said drain region;
• at least one source contact that is conductively coupled to said metal-1 field plate;
• and
• a conductive plate structure that is conductively coupled to said metal-1 field plate, wherein at least a first portion of said conductive plate structure extends downward toward said substrate and lands on said silicide block layer in said area between said gate electrode and said drain region.