Flash memory devices and methods for fabricating same

A memory device comprising:

• a plurality of first gate stacks and a plurality of second gate stacks overlying a substrate, wherein the plurality of first gate stacks are disposed in a linear manner along a length of the substrate and the plurality of second gate stacks are disposed in a linear manner along the length of the substrate parallel to the plurality of first gate stacks;
• a conductor disposed within a trench in the substrate between the plurality of first gate stacks and the plurality of second gate stacks, wherein the conductor and the trench extend along the length of the substrate;
• and
• a first impurity doped region disposed within the substrate and underlying the trench and the conductor, wherein the first impurity doped region extends along the length of substrate.

A memory device comprising:

• a plurality of first gate stacks and a plurality of second gate stacks overlying a substrate, wherein the plurality of first gate stacks are disposed in a linear manner along a length of the substrate and the plurality of second gate stacks are disposed in a linear manner along the length of the substrate parallel to the plurality of first gate stacks;
• a first impurity doped region disposed within the substrate between the plurality of first gate stacks and the plurality of second gate stacks along the length of substrate;
• a second impurity doped region disposed within the substrate between the plurality of first gate stacks and the plurality of second gate stacks along the length of substrate, wherein the second impurity doped region is disposed deeper within the substrate than the first impurity doped region;
• and
• a conductor disposed overlying the substrate between the plurality of first gate stacks and a plurality of second gate stacks, wherein the conductor extends along the length of the substrate and is in electrical contact with the first and second impurity doped regions.