DRAM Cells and Methods of Forming Silicon Dioxide

A method of forming silicon dioxide, comprising:

• forming an opening extending into monocrystalline silicon, the opening exposing multiple crystallographic planes of the monocrystalline silicon;
• forming silicon dioxide along the multiple crystallographic planes along an interior surface of the opening utilizing a first treatment temperature of less than or equal to about 1000° C.;
• and
• annealing an interface between the silicon dioxide and the monocrystalline silicon utilizing a second treatment temperature which is at least about 1050° C.

A method of forming a transistor, comprising:

• forming a trench extending into monocrystalline silicon, the trench exposing multiple crystallographic planes of the monocrystalline silicon;
• forming silicon dioxide along the multiple crystallographic planes along an interior surface of the trench utilizing a first treatment temperature of less than or equal to about 1000° C.;
• annealing an interface between the silicon dioxide and the monocrystalline silicon utilizing a second treatment temperature which is at least about 1050° C.;
• forming a transistor gate within the trench and spaced from the monocrystalline silicon by the silicon dioxide;
• and
• forming a pair of source/drain regions within the monocrystalline silicon;
• with the source/drain regions being on opposing sides of the transistor gate from one another.

A DRAM cell comprising:

• a gate spaced from a silicon-containing channel region by silicon dioxide;
• source/drain regions on opposing sides of the gate relative to one another;
• a capacitor coupled to one of the source/drain regions;
• wherein the silicon dioxide being formed utilizing the two stages of (1) growing silicon dioxide across a silicon-containing surface utilizing a first treatment temperature of less than or equal to about 1000° C., and (2) annealing an interface between the silicon dioxide and the silicon-containing surface utilizing a second treatment temperature which is at least about 1050° C.;
• wherein the gate has a width of less than or equal to about 40 nanometers;
• and
• wherein the DRAM cell is within an array having a time to 200 bit per die failure of at least about 400 milliseconds for charge retention.