Multiprocessor system and method for managing cache memory thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsIL PARK, YOUNG PYO JOO
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Abstract
A multiprocessor system includes a plurality of master devices, at least one slave device, and a system bus connecting the master devices to the at least one slave device. At least one of the master devices includes at least one cache memory, and the system bus processes a data write or data read request corresponding a transaction issued to the slave device from at least one of the master devices prior to termination of a snooping operation on the master devices.
Claims20
A multiprocessor system comprising:
- a plurality of master devices, wherein at least one of the master devices comprises at least one cache memory;
- at least one slave device;
- and
- a system bus configured to connect the master devices to the at least one slave device,
- wherein the system bus processes a data write or data read request corresponding to a transaction issued to the slave device from at least one of the master devices prior to termination of a snooping operation on the master devices.
A method of managing a cache memory of a multiprocessor system comprising:
- issuing a transaction to a slave device of the system from at least one of a plurality of master devices of the system;
- processing, by a system bus of the system, a data read or data write request corresponding to the transaction;
- and
- snooping, by the system bus, the master device from which the transaction is not issued among the master devices,
- wherein the processing of the data read or data write request is performed prior to termination of the snooping of the master device.
A method of managing a cache memory of a system by a system bus of the system, the method comprising:
- receiving by the system bus, a write request from a first master device of the system;
- writing by the system bus, first data of the write request to the slave device;
- after the writing, determining by the system bus, whether second data corresponding to the first data is present within the cache memory of second master device of the system;
- and
- marking by the system bus, the present data in the cache memory as invalid.
Dependencies are inferred from the claim text.