Apparatus and method for implementing a multi-level memory hierarchy over common memory channels

A computer system comprising:

• a processor having a plurality of cores for executing instructions and processing data and one or more processor caches for caching instructions and data according to a first cache management policy;
• a first memory channel comprising a first set of address/control and data lines coupled to the processor;
• a second memory channel comprising a second set of address/control and data lines coupled to the processor;
• a first first-level memory and a second first-level memory each having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed, the first first-level memory coupled to the first memory channel and the second first-level memory coupled to the second memory channel;
• and
• a first second-level memory communicatively coupled to the first memory channel, and a second second-level memory communicatively coupled to the second memory channel, the first and second second-level memories having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the first and second second-level memories maintain content if power is removed, wherein at least a portion of the first first-level memory is configured as a cache for instructions and data stored in the first second-level memory and at least a portion of the second first-level memory is configured as a cache for instructions and data stored in the second second-level memory.