Division circuit and memory controller

A division circuit comprising:

• a separation circuit configured to separate a dividend into k-bit segments starting from a lowest bit of the dividend where k is integer multiple of n, and output h/k separated dividends, wherein the dividend is h-bit long that is longer than a specific divisor of 2n−1 where n is an integer and n≧2;
• a first output circuit configured to output, for every separated dividend, a remainder and a 2k-bit quotient that are obtained by dividing by the specific divisor a separated dividend with 0s added where the number of 0s is equal to integer multiple of k;
• a second output circuit configured to output, for every separated dividend, a first bit sequence that includes an upper k-bit sequence of the 2k-bit quotient, and a second bit sequence that includes i sets of lower k bits of the 2k-bit quotient, wherein a position of each separated dividend counted from a separated dividend having the lowest bit is called i where i=0 to h/k−1;
• a quotient addition circuit configured to add composite sequences in each of which the first bit sequence is placed at upper bits and the second bit sequence is placed at lower bits;
• a remainder addition circuit configured to calculate sum of remainders output from the first output circuit;
• a remainder division circuit configured to divide the sum of remainders by the specific divisor and output a quotient and a remainder;
• and
• a carried value addition circuit configured to add an output from the quotient addition circuit and the quotient output from the remainder division circuit.

A memory controller that controls access to memory modules that are separated into 2n−1 channels where n is an integer and n≧2, the memory controller comprising:

• a separation circuit configured to separate a dividend into k-bit segments starting from a lowest bit of the dividend where k is integer multiple of n, and output h/k separated dividends, wherein the dividend is h-bit long that is longer than a specific divisor that is the number of channels;
• a first output circuit configured to output, for every separated dividend, a remainder and a 2k-bit quotient that are obtained by dividing by the specific divisor a separated dividend with 0s added where the number of 0s is equal to integer multiple of k;
• a second output circuit configured to output, for every separated dividend, a first bit sequence that includes an upper k-bit sequence of the 2k-bit quotient, and a second bit sequence that includes i sets of lower k bits of the 2k-bit quotient, wherein a position of each separated dividend counted from a separated dividend having the lowest bit is called i where i=0 to h/k−1;
• a quotient addition circuit configured to add composite sequences in each of which the first bit sequence is placed at upper bits and the second bit sequence is placed at lower bits;
• a remainder addition circuit configured to calculate sum of remainders output from the first output circuit;
• a remainder division circuit configured to divide the sum of remainders by the specific divisor and output a quotient and a remainder;
• a carried value addition circuit configured to add an output from the quotient addition circuit and the quotient output from the remainder division circuit;
• and
• a selection circuit configured to select one channel from among the 2n−1 channels based on the remainder output from the remainder division circuit and select, based on the result output from the carried value addition circuit, one memory module from among the memory modules that belongs to the one channel.