Configuration memory

A configuration memory comprising:

• first and second data lines;
• first and second control lines;
• a first memory pair which comprises a first nonvolatile memory transistor of which gate terminal is connected to the first control line, of which drain terminal is connected to the first data line, and of which source terminal is connected to the common node, and a second nonvolatile memory transistor of which gate terminal is connected to the first control line, of which drain terminal is connected to the second data line, and of which source terminal is connected to the common node;
• a second memory pair which comprises a third nonvolatile memory transistor of which gate terminal is connected to the second control line, of which drain terminal is connected to the first data line, and of which source terminal is connected to the common node, and a fourth nonvolatile memory transistor of which gate terminal is connected to the second control line, of which drain terminal is connected to the second data line, and of which source terminal is connected to the common node;
• and
• a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

A configuration memory comprising:

• first and second data lines;
• a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line
• a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line;
• an N-channel type FET of which gate terminal is connected to the common node, of which source terminal is connected to a ground node, and of which drain terminal is connected to a configuration data input node;
• a flip-flop circuit which are connected between the configuration data input node and a configuration data output node;
• and
• a P-channel type FET,
• wherein a control signal is input to a gate terminal of the P-channel type FET, a source terminal of the P-channel type FET is connected to a power supply node, and a drain terminal of the P-channel type FET is connected to the configuration data input node.

A configuration memory comprising:

• first and second data lines;
• a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line;
• a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line;
• an inverter of which input terminal is connected to the common node;
• a transfer gate which is connected between a configuration data input node and an output terminal of the inverter;
• and
• a flip-flop circuit which are connected between the configuration data input node and a configuration data output node.