Back to results
US 2013/0258780 A1Published application
Method of programming selection transistors for nand flash memory
AssigneeElpida Memory, Inc.
InventorsOsama Khouri, Simone Bartoli
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.
Claims20
A method comprising:
- providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors;
- applying a first program voltage to the selection line;
- and
- applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.
1 more element
A method comprising:
- performing an erase operation on a non-volatile memory cell that is coupled to a selection transistor;
- the performing the erase operation comprising:
- applying a first voltage to the selection transistor;
- and
- applying a second voltage to the selection transistor when the selection transistor has not been shifted to an program condition due to the applying the first voltage, the second voltage being larger than the first voltage.
2 more elements
A device comprising:
- a non-volatile memory array including a cell and a selection transistor coupled to the cell;
- and
- a first circuit supplying first and second program voltages, the first voltage being supplied to the selection transistor in order to shift the selection transistor to a program condition, the second voltage being supplied to the selection transistor when the selection transistor has not been shifted to the program condition due the supplying of the first voltage, the second voltage being larger than the first voltage.
Dependencies are inferred from the claim text.