US 2013/0258762 A1Published application

Reference cell configuration for sensing resistance states of mram bit cells

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYu-Der CHIH, Chun-Jung LIN, Kai-Chun LIN, Hung-Chang YU

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Abstract

A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

Claims20

Dependent claims

A digital memory, comprising:

at least one magneto-resistive memory cell comprising a magnetic tunnel junction element with a pinned magnetic layer having a permanently oriented magnetic field and a free magnetic layer having a magnetic field component that is changeably alignable parallel to magnetic field of the pinned layer, in a state of low electrical resistance, and anti-parallel to the magnetic field of the pinned layer in a state of high electrical resistance, wherein a data value is changeably stored in the cell by alignment of the magnetic field of the free layer relative to the pinned layer, and is detectable by differences in a cell value of an electrical parameter produced by the memory cell when subjected to a cell bias current;
a reference circuit comprising a high resistance reference and a low resistance reference, wherein the reference circuit produces an electrical parameter having a reference value when subjected to a reference bias current;
a comparator circuit coupled to compare the reference value versus the cell value, the comparator having an output reading out the data value corresponding to the cell value being greater than or less than the reference value;
wherein the reference value represents a value falling between values of the electrical parameter produced by the memory cell in the states of high and low electrical resistance.

1 more element

An improved MRAM memory configuration having an array of magnetic tunnel junction bit cells with free and pinned magnetic layers, the bit cells being writable to parallel and anti-parallel magnetic field alignments of the layers for carrying a logic value in one of a low resistance and high resistance state, wherein the logic value of a bit cell is read out by comparing a resistance of the bit cell as coupled into a bias circuit, versus a reference resistance, using a comparator responsive to one of voltage and current, wherein the comparator has inputs coupled to the bit cell and to a reference circuit that provides the reference resistance, wherein the improvement comprises:

the reference circuit comprises two reference magnetic tunnel junction elements that are set at low resistance and a high resistance respectively, and the reference resistance falls between high and low resistances of the bit cell in the high and low resistance states;
wherein the reference magnetic junction elements in the reference circuit are arranged along a bias path in a bias circuit that substantially parallels the bias circuit coupled to the bit cell;
wherein the reference magnetic junction elements in the reference circuit are both oriented in the bias path at a polarity that prevents risk of read-disturb errors.

Dependencies are inferred from the claim text.