Dual-port sram with bit line clamping

A memory, comprising:

• a plurality of bit lines;
• a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
• a multiplexer for selectively coupling the driven bit line to the internal node;
• and
• a clamping circuit operable to clamp the plurality of bit lines to a clamping voltage, wherein the clamping circuit is further operable to unclamp the selected bit line driven by the write driver during the write operation.

A memory, comprising:

• a plurality of bit lines;
• a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation, the write driver coupled to an internal node;
• a multiplexer for selectively coupling the driven bit line to the internal node;
• and
• a clamping circuit operable to clamp the internal node to a clamping voltage, wherein the clamping circuit is further operable to unclamp the internal node during the write operation.