Clock-delayed domino logic circuit and devices including the same

A data processing device comprising:

• a clock generator configured to generate a clock signal;
• a data source configured to output data;
• and
• a clock-delayed domino logic circuit,
• wherein the clock-delayed domino logic circuit includes:
• a precharge circuit configured to control connection between a first node and a dynamic node in response to the clock signal;
• an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal;
• a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on the data;
• and
• a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.

An electronic device comprising:

• a processor including a data processing device;
• and
• a wireless network interface connected to the processor through an interface control block,
• wherein the data processing device includes:
• a clock generator configured to generate a clock signal;
• a data source configured to output data;
• and
• a clock-delayed domino logic circuit,
• wherein the clock-delayed domino logic circuit includes:
• a precharge circuit configured to control connection between a first node and a dynamic node in response to the clock signal;
• an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal;
• a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on the data;
• and
• a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.