Inter-die connection within an integrated circuit formed of a stack of circuit dies
AssigneeArm Limited
InventorTeresa Louise Mclaurin
Life of this patent
Estimating the term…
Abstract
An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.
Claims15
An integrated circuit comprising:
- a plurality of circuit dies stacked together, each of said plurality of circuit dies having a substrate layer with a layer of processing circuitry formed thereupon;
- wherein
- at least one of said plurality of circuit dies has a plurality of vias extending to a face of said at least one of said plurality of dies;
- at least one of said plurality of circuit dies has an inter-die routing layer providing a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via position at which one of said vias extends to said face and a connection position at which a conductive connection is made to an adjacent circuit die of said plurality of circuit dies;
- and
- said vias in said at least one of said plurality of circuit dies have a via placement pattern, said connection positions in said adjacent circuit die have a connection position placement pattern, said via placement pattern is different from said connection position placement pattern and said inter-die routing layer provides said conduction paths to bridge gaps between via positions and connection positions.
An integrated circuit as claimed in claim 2, wherein said plurality of vias extend through one of:
- (i) said substrate layer;
- (ii) said layer of processing circuitry;
- and (iii) said substrate layer and said layer of processing circuitry.
An integrated circuit as claimed 2, wherein said plurality of vias extend through said substrate layer and said inter-die routing layer is formed in an outer face of said substrate layer.
An integrated circuit as claimed 1, wherein said adjacent circuit die comprises a substrate layer having a layer of processing circuitry formed thereupon and said inter-die routing layer is formed in an outer face of said layer of processing circuitry.
An integrated circuit comprising:
- a plurality of circuit dies stacked together, each of said plurality of circuit dies having a substrate layer with a layer of processing circuitry formed thereupon;
- wherein
- at least one of said plurality of circuit dies has a plurality of vias extending to a face of said at least one of said plurality of dies;
- at least one of said plurality of circuit dies has an inter-die routing layer providing a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via position at which one of said vias extends to said face and a connection position at which a conductive connection is made to an adjacent circuit die of said plurality of circuit dies;
- and
- said connection position is displaced from said via position by a distance greater than a manufacturing tolerance in locating said connection position relative to said via position.
An integrated circuit comprising:
- a plurality of circuit dies stacked together, each of said plurality of circuit dies having a substrate layer with a layer of processing circuitry formed thereupon;
- wherein
- at least one of said plurality of circuit dies has a plurality of vias extending to a face of said at least one of said plurality of dies;
- at least one of said plurality of circuit dies has an inter-die routing layer.
A method of connecting adjacent circuit dies in a stack of circuit dies each having a substrate layer with a layer of processing circuitry formed thereupon, said method comprising the steps of:
- forming vias extending through to a face of a first circuit die;
- and
- forming an inter-die routing layer to provide a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via formed in said first circuit die and a connection position within a second circuit die adjacent said first circuit die within said stack;
- wherein
- said vias in said first circuit die have a via placement pattern, said connection positions in said second circuit die have a connection position placement pattern, said via placement pattern is different from said connection position placement pattern, and said inter-die routing layer provides said conduction paths to bridge gaps between through via positions and connection positions.
A method of connecting adjacent circuit dies in a stack of circuit dies each having a substrate layer with a layer of processing circuitry formed thereupon, said method comprising the steps of:
- forming vias extending through to a face of a first circuit die;
- and
- forming an inter-die routing layer to provide a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via formed in said first circuit die and a connection position within a second circuit die adjacent said first circuit die within said stack;
- wherein
- said connection position is displaced from via position by a distance greater than a manufacturing tolerance in locating said connection position relative to said via position.
A method of connecting adjacent circuit dies in a stack of circuit dies each having a substrate layer with a layer of processing circuitry formed thereupon, said method comprising the steps of:
- forming vias extending through to a face of a first circuit die;
- and
- forming an inter-die routing layer to provide a plurality of conduction paths, at least one of said plurality of conduction paths extending between a via formed in said first circuit die and a connection position within a second circuit die adjacent said first circuit die within said stack.
Dependencies are inferred from the claim text.