Semiconductor package

A device, comprising:

• a semiconductor chip including:
• a semiconductor substrate;
• an interlayer insulating layer overlying the semiconductor substrate;
• a chip pad overlying the interlayer insulating layer;
• a plurality of first circuit patterns extending through the interlayer insulating layer, the plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor substrate;
• a first via electrically connecting the chip pad to the first circuit patterns;
• and
• a conductive bump overlying the chip pad,
• wherein the chip pad has a central region in contact with the conductive bump and a peripheral region substantially surrounding the central region, and wherein the first via is connected to the peripheral region of the chip pad.

A semiconductor package, comprising:

• a circuit substrate;
• a semiconductor chip including a chip pad;
• and
• a connection pattern electrically connecting the circuit substrate with the semiconductor chip,
• wherein the semiconductor chip comprises a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns, and
• wherein the first via is connected to the chip pad outside of a region arranged directly beneath the connection pattern.