Three dimensional floating gate nand memory

A memory array comprising:

• at least two vertical stacks of memory cells, each vertical stack comprising:
• at least two memory cells, the at least two memory cells positioned along a first axis, each memory cell comprising:
• a channel;
• a first insulator;
• a floating gate;
• a second insulator;
• and
• a control gate
• wherein the first insulator is positioned between the control gate and the floating gate, the second insulator is positioned between the floating gate and the channel, and the control gate, the first insulator, the floating gate, the second insulator and the channel are positioned along a second axis,
• wherein the first axis and the second axis are perpendicular to each other;
• and at least one vertical isolation structure positioned between the first and the second memory cell;
• and
• at least one horizontal isolation structure, wherein the at least one horizontal isolation structure isolates a first vertical stack of memory cells from a second vertical stack of memory cells.

A method of making a memory array, the method comprising:

• depositing a bilayer stack of alternating insulating material and floating gate material;
• etching a first void in the stack;
• depositing a first insulating material on at least the walls of the first void forming a second void;
• depositing channel material in the second void;
• etching a third void in the stack, the third void being substantially circular and surrounding the channel material;
• selectively etching portions of the polysilicon layers adjacent the third void forming fourth voids, wherein the fourth voids are generally orthogonal to each other;
• depositing a second insulating material on the surfaces of the fourth voids;
• depositing control gate material on the second insulating material, forming a sixth void;
• and
• depositing isolating material in the sixth void.