Electrically erasable programmable non-volatile memory

A method of fabricating a floating-gate p-type MOSFET, a p-type MOSFET and an analog capacitor concurrently comprising:

• forming a first, a second, a third, a fourth, and a fifth thick oxide region on an p-type substrate;
• implanting a first and a second Pwell region below the first and the second thick oxide region respectively and a third and a fourth Pwell region below the third and the fourth thick oxide region respectively;
• implanting a first Nwell region between the first and the second thick oxide regions and a second Nwell region between the third and the fourth thick oxide region;
• growing a gate insulation on the first and second Nwell regions and on the fifth thick oxide region;
• depositing poly-silicon on the gate insulation;
• etching the poly-silicon to form a first, a second and a third poly-silicon portion;
• forming oxide side-walls on sides of the first, the second and the third poly-silicon portions;
• forming nitride side-walls on the oxide side-walls;
• implanting an p-type dopant into the first and the second Nwells forming a first and a second source and a first and a second drain;
• forming a silicide-blocking layer over the first poly-silicon portion, the oxide side-walls of the first poly-silicon portion, the nitride walls of the first poly-silicon portion, a first portion of the first source and a first portion of the first drain;
• forming a silicide on a second portion of the first source, on a second portion of the first drain, on a first portion of the second source, on a first portion of the second drain, on the second poly-silicon portion, and on the third poly-silicon portion;
• forming a nitride layer over the silicide-blocking layer and over the silicide on the third poly-silicon portion;
• forming a conductive layer over the nitride layer;
• forming metal contacts on the second portion of the first source, the second portion of the first drain, the first portion of the second source, and the first portion of the second drain.

A method of fabricating a floating-gate n-type MOSFET comprising:

• forming a first and a second thick oxide region on an n-type substrate;
• implanting a first and a second Nwell region below the first and second thick oxide region respectively;
• implanting an Pwell region between the first and second thick oxide regions and the first and second Nwells;
• growing a gate insulation on the Pwell region;
• depositing poly-silicon on the gate insulation;
• etching the poly-silicon to form a poly-silicon gate;
• forming oxide side-walls on sides of the poly-silicon gate;
• forming nitride side-walls on the oxide side-walls;
• implanting an n-type dopant into the Pwell on both sides of the nitride side-walls forming a source and a drain;
• forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain;
• forming a silicide on a second portion of the source and on a second portion of the drain;
• forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain;
• forming a conductive layer over the nitride layer;
• forming metal contacts on the second portion of the source and the second portion of the drain.