Estimating delay deterioration due to device degradation in integrated circuits

A system for estimating delay deterioration in an integrated circuit comprising:

• a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit;
• a netlist generator for generating an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations;
• and
• a timing analyzer for performing a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.

A computer readable storage medium comprising a computer readable program for estimating delay deterioration in an integrated circuit, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

• estimating degradation over each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit;
• estimating a change in timing delay for each of the one or more lifetimes of each device directly from each of the estimated degradations of the at least one characteristic of each device;
• and
• performing a timing analysis for each of the estimated changes in timing delay to determine circuit path delays over each of the one or more lifetimes.