Scan test circuit, test pattern generation control circuit, and scan test control method

A test pattern generation control circuit comprising:

• a test pattern generation mode control unit that is supplied with a clock identical with the clock supplied to a plurality of flip-flop circuits forming a clock domain operating according to the same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test;
• and
• a scan enable signal output unit that outputs a first scan enable signal to the plurality of flip-flop circuits, the first scan enable signal being determined based on the test pattern generation mode.

A scan test control method comprising:

• supplying a clock identical with the clock supplied to a plurality of flip-flop circuits that form a clock domain operating according to the same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test;
• and
• outputting a scan enable signal to the plurality of flip-flop circuits, the scan enable signal being determined based on the test pattern generation mode.

A scan test control method comprising:

• supplying a clock identical with the clock supplied to a plurality of flip-flop circuits that form a clock domain operating according to the same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test;
• and
• outputting a scan enable signal to the plurality of flip-flop circuits to stop supply of an unwanted capture clock signal to the plurality of flip-flop circuits, the scan enable signal being determined based on the test pattern generation mode.