Access method and multi-core processor system

A multi-core processor system comprising:

• a first CPU that executes a first application;
• and
• a peripheral device that is accessed by the first application, wherein
• the peripheral device is connected to a virtual register that includes a timer, a first detecting circuit, a second detecting circuit, and a register,
• the timer responds to the access and measures an access time period,
• the first detecting circuit compares the access time period and the predetermined time period, and
• the second detecting circuit, when the access time period exceeds the predetermined time period, outputs a detection signal and with respect to data to be written from the first CPU into the peripheral device, stops a writing of the data into the register.