Semiconductor integrated circuit device and system using the same

A semiconductor integrated circuit device which operates a plurality of threads each as a software execution unit, two threads out of the threads being specific software for accessing a memory, comprising:

• a first buffer for storing an address on a memory access;
• a second buffer for storing read data obtained by a memory access;
• and
• a first comparison circuit for comparing the address on the memory access with an address stored in the first buffer,
• wherein in the case where a read access to the memory is performed in a first thread out of the two threads, the address on the read access is stored in the first buffer,
• wherein, in the case where a read access to the memory is performed in a second thread out of the two threads, the address and the address stored in the first buffer are compared by the first comparison circuit and,
• wherein, in response to a mismatch from the first comparison circuit, a process corresponding to a failure is performed.

A semiconductor integrated circuit device which operates while switching a plurality of threads each as a software execution unit,

• two threads out of the threads being same software for accessing a memory, comprising:
• a first buffer for storing an address on a memory access;
• a third buffer for storing data to be written in a memory;
• a first comparison circuit for comparing the address on the memory access with an address stored in the first buffer;
• and
• a second comparison circuit for comparing data to be written in a memory and data stored in the third buffer,
• wherein in the case where a write access to the memory is performed in a first thread out of the two threads, the address on the write access is stored in the first buffer and data to be written is stored in the third buffer,
• wherein, in the case where a write access to the memory is performed in a second thread out of the two threads, the address and the address stored in the first buffer are compared by the first comparison circuit, the data to be written and write data stored in the third buffer are compared by the second comparison circuit and,
• wherein, in response to a mismatch from at least one of the first and second comparison circuits, a process corresponding to a failure is performed.