Clock generation for timing communications with ranks of memory devices

A memory controller, comprising:

• a clock generator to generate a first clock signal;
• and
• a timing circuit to generate a second clock signal from the first clock signal to time communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank, the timing circuit comprising:
• a first phase adjuster to generate an intermediate clock signal by adjusting a phase of the first clock signal;
• a plurality of respective storage elements, each to store calibration data associated with a respective memory device in a respective rank and configured to be selectively coupled to the first phase adjuster when the memory controller is to communicate with the respective memory device in the respective rank, wherein the first phase adjuster is to adjust the phase of the first clock signal based on the calibration data stored in the selectively coupled storage element;
• and
• a second phase adjuster to generate the second clock signal by adjusting a phase of the intermediate clock signal based on timing adjustment data associated with feedback from one or more of the plurality of memory devices in the respective ranks

A memory controller, comprising:

• a clock generator to generate a first clock signal;
• a first phase adjuster to generate a second clock signal by adjusting a phase of the first clock signal, the second clock signal to time communications with any of a plurality of memory devices in respective ranks;
• a plurality of respective storage elements, each to store calibration data associated with a respective memory device in a respective rank and configured to be selectively coupled to the first phase adjuster when the memory controller is to communicate with the respective memory device in the respective rank, wherein the first phase adjuster is to adjust the phase of the first clock signal based on the calibration data stored in the selectively coupled storage element;
• calibration circuitry to perform calibration for a first memory device in a first rank and, in response, to determine an amount by which to adjust calibration data associated with the first memory device in a first storage element of the plurality of storage elements;
• and
• adjustment circuitry to adjust calibration data associated with the second memory device in a second storage element of the plurality of respective storage elements by the determined amount.

A method of controlling memory devices, comprising:

• at a memory controller coupled to memory devices in a plurality of ranks, including a first memory device in a first rank and a second memory device in a second rank:
• generating a first clock signal;
• adjusting a phase of the first clock signal to generate a second clock signal, the adjusting based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device;
• and
• timing communications with the second memory device, in accordance with the second clock signal.

A method of controlling memory devices, comprising:

• at a memory controller coupled to memory devices in a plurality of ranks, including a first memory device in a first rank and a second memory device in a second rank:
• performing a calibration of first timing for communication between the memory controller and the first memory device;
• performing a calibration of second timing for communication between the memory controller and the second memory device;
• communicating with the first memory device in accordance with the first timing;
• while communicating with the first memory device, determining timing adjustments based on feedback from the first memory device and modifying the first timing based on the timing adjustments;
• communicating with the second memory device in accordance with the second timing as modified by the timing adjustments;
• and
• while communicating with the second memory device, determining additional timing adjustments based on feedback from the second memory device and modifying the second timing based on the additional timing adjustments.