Sequencer system and control method therefor

Abstract

A sequencer system includes a plurality of units, a backplane on which the units are mounted, bus communication lines for data transmission and reception among the units, a clock generation unit that generates a fixed-cycle clock signal having an arbitrary cycle, and an electric signal line provided separately from the bus communication lines, to transfer the fixed-cycle clock signal from the clock generation unit to the units via the backplane. Each of the units includes a processor that controls the unit, and an interrupt-signal control unit that generates an interrupt signal corresponding to the fixed-cycle clock signal. The processor uses the interrupt signal to synchronize control timings of the units.

Dependencies are inferred from the claim text.