US 2013/0254576 A1Published application

Multiprocessor system and method of controlling power

AssigneeKabushiki Kaisha Toshiba

InventorTakeshi Kodaka

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Abstract

According to one embodiment, a multiprocessor system includes a plurality of processors, a power supply device and a shared memory. The shared memory includes a thread pool and a thread queue. In the thread pool, threads each having waiting events are registered in association with the numbers of the waiting events. In the thread queue, threads having no waiting event are registered. One or more first processors acquire first thread from the thread queue and execute the first thread. A second processor updates the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event. A third processor operates supply of power to the first processors individually based on the number of threads in the thread queue and the number of waiting events.

Claims20

Dependent claims

A multiprocessor system comprising:

a plurality of processors;
a power supply device that individually supplies power to the processors;
and
a shared memory that stores a plurality of threads, each thread being executed by one of the plurality of processors,
wherein the shared memory includes:
a thread pool in which threads each having waiting events are registered in association with the numbers of the waiting events;
and
a thread queue in which threads having no waiting event are registered, and
wherein the plurality of processors include:
one or more first processors each acquiring a first thread from the thread queue and executing the first thread when power is supplied from the power supply device;
a second processor that updates the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event and registers the second thread to the thread queue when the number of the waiting events of the second thread is zero;
and
a third processor that individually stops or resumes supply of power from the power supply device to the first processors based on the number of threads that are registered in the thread queue and the number of threads of which the number of waiting events is a first threshold value or less.

10 more elements

A method of controlling power that is implemented by a multiprocessor system that includes a plurality of processors, a power supply device that individually supplies power to the processors, and a shared memory that stores a plurality of threads, each thread being executed by one of the processors, comprising:

registering threads each having the number of waiting events that are stored in the shared memory in a thread pool in association with the numbers of waiting events;
registering threads each not having the number of waiting events that are stored in the shared memory in a thread queue;
acquiring a first thread from the thread queue and executing the acquired first thread by using a processor out of the plurality of processors to which power is supplied from the power supply device;
updating the number of waiting events of a second thread, which is registered in the thread pool, having completion of required procedure for the second thread by the first thread as a waiting event;
registering the second thread to the thread queue when the number of the waiting events of the second thread is zero;
calculating a set value of the number of processors based the number of threads that are registered in the thread queue and the number of threads of which the number of waiting events is a first threshold value or less;
and
individually stopping or resuming supply of power from the power supply device to the processors such that the number of processors to which power is supplied is the same as the set value of the number of processors.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/727,866Filed 27 Dec 2012
Priority: JP 2012-06672623 Mar 2012
Published: 26 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/3228
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring task completion, e.g. by use of idle timers, stop…
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing

Family

US 9,047,088 B2Related patent
US 2013/0254576 A1This patent

From the US filing history. Foreign family members aren’t listed.

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