US 2013/0254569 A1 · INDIVIDUAL CORE VOLTAGE MARGINING

Abstract

Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.

Claims21

Dependent claims

An apparatus comprising:

a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by a voltage offset value programmed by an offset code received at the control input of the voltage offset block;
and
a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage offset register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage offset value of a selected voltage offset block, at the control output coupled to the selected voltage offset block.

A system comprising:

a chipset;
and
a multi-core processor coupled to the chipset, with the multi-core processor including voltage offset blocks configured to offset voltage levels provided to each core processor in the multi-core processor to reduce power consumption.

Dependencies are inferred from the claim text.

Individual core voltage margining

Life of this patent

Individual core voltage margining

Life of this patent

Abstract

Claims21