Controlling a processor cache using a real-time attribute
OwnerJames A. Coleman, Durgesh Srivastavainventors
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Abstract
A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed.
Claims22
A processor device comprising:
- a cache;
- a cache controller coupled to the cache to manage the replacement of a plurality of cache lines in the cache, in accordance with a replacement policy in which each of the cache lines has an associated age indicator;
- and
- a storage location that is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region, wherein upon a cache miss of an address that lies in the real time region, the cache controller is to respond by loading content at said address into a cache line and then prevent the cache line from aging as would a cache line that is in the cacheable region.
A method for controlling a processor cache, comprising:
- receiving a request for content at a memory address, and in response accessing a processor cache that has a replacement policy, to generate one of a cache hit and a cache miss for the memory address;
- in response to the cache miss, loading content at the memory address into a cache line;
- performing a lookup of the memory address to produce an attribute that is associated with the memory address;
- marking the cache line with an aging indicator that is based on the attribute, wherein the marked aging indicator is one of a slow aging indicator and a normal aging indicator;
- and
- in response to marking with the slow aging indicator, preventing the cache line from aging as would another cache line that is marked with the normal aging indicator.
A computer system comprising:
- main memory having stored therein a program;
- and
- a processor device having a cache coupled to the main memory, a cache controller coupled to the cache to manage the replacement of a plurality of cache lines in the cache, in accordance with a replacement policy, and storage that is to be configured by the program while being executed by the processor device to define a memory map having a cacheable region, an un-cacheable region, and a real time region, wherein upon a cache miss of an address that lies in the real time region, the cache controller is to respond by loading content at said address into a cache line and wherein the loaded cache line ages more slowly than a cache line that is in the cacheable region.
An article of manufacture comprising:
- a machine-readable storage medium having stored therein a program that when executed by a processor device configures a control register of the processor device to define a real time region in a memory map for the processor device, wherein the memory map can also have a cacheable region and an un-cacheable region defined in the control register, and wherein the real time region contains code and data of an interrupt service routine that is part of the program.
Dependencies are inferred from the claim text.