Systems and methods for cache line replacement
AssigneeQUALCOMM Incorporated
InventorsAjay Anant Ingle, Erich James Plondke, Lucian Codrescu
Life of this patent
Estimating the term…
Abstract
A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.
Claims20
A computer readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
- receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value;
- and
- assign the index value as an identifier value in response to receiving the cache invalidate by index instruction, wherein the identifier value indicates a cache line for replacement.
A computer readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
- receive a cache instruction to be executed, wherein an identifier value is selected from an index value, an encoded way value, or an incrementer output value, wherein the identifier value is selected based on the cache instruction, the identifier value indicates a cache line for replacement, and, when the cache instruction comprises a cache invalidate by index instruction, the index value is selected as the identifier value.
A computer readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
- assign one of an index value, an encoded way value, or an incrementer output value as an identifier value based on a cache instruction, wherein the identifier value indicates a cache line for replacement, and wherein the index value is assigned as the identifier value in response to the cache instruction being a cache invalidate by index instruction.
Dependencies are inferred from the claim text.