Speculative cache modification

A system comprising:

• a display unit;
• and
• an integrated circuit, wherein the integrated circuit comprises:
• a data bus,
• a cache communicably interfaced with the data bus;
• a pipeline communicably interfaced with the data bus, the pipeline to receive a store instruction corresponding to a cache line to be written to cache,
• caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline, and
• cache line validation logic to determine if the cache line written into the cache is valid or invalid, wherein the cache line validation logic to invalidate the cache line speculatively written into the cache when determined invalid and wherein the store instruction is allowed to retire from the pipeline when the cache line is determined valid.

A tablet computing device comprising:

• a display unit;
• and
• an integrated circuit, wherein the integrated circuit comprises:
• a data bus,
• a cache communicably interfaced with the data bus;
• a pipeline communicably interfaced with the data bus, the pipeline to receive a store instruction corresponding to a cache line to be written to cache,
• caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline, and
• cache line validation logic to determine if the cache line written into the cache is valid or invalid, wherein the cache line validation logic to invalidate the cache line speculatively written into the cache when determined invalid and wherein the store instruction is allowed to retire from the pipeline when the cache line is determined valid.

A method in an integrated circuit, the method comprising:

• receiving a store instruction at a pipeline of the integrated circuit, the store instruction corresponding to a cache line to be written to a cache;
• writing the cache line to the cache of the integrated circuit via a speculative cache write before the store instruction retires from the pipeline;
• determining if the cache line speculatively written into the cache is valid or invalid;
• invalidating the cache line in the cache when the cache line is determined to be invalid;
• and
• allowing the store instruction to retire from the pipeline when the cache line is determined to be valid.