Memory refresh method and devices
AssigneeRambus Inc.
InventorsRichard Perego, Thomas Vogelsang, John Brooks
Life of this patent
Estimating the term…
Abstract
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
Claims31
An integrated circuit device that controls a memory device, the integrated circuit device comprising:
- a circuit to provide:
- a bank address, wherein the bank address identifies a bank of a plurality of banks in a memory device;
- a first row address that identifies a first row within the bank of the memory device for a memory access;
- a second row address that identifies a second row within the bank of the memory device to perform a refresh operation;
- and
- an interface to output the bank address, the first row address, and the second row address to the memory device.
(canceled)
(canceled)
(canceled)
(canceled)
(canceled)
A memory device comprising:
- a plurality of banks, each bank of the plurality of banks having a plurality of storage cells;
- an interface to receive a command that specifies a memory access to a predetermined bank of the plurality of banks;
- a first plurality of sense amplifiers to sense, in response to the command that specifies the memory access, a first row of memory cells in the predetermined bank;
- and
- a second plurality of sense amplifiers to refresh a second row of memory cells in the predetermined bank, wherein the second plurality of sense amplifiers refreshes the second row of memory cells while the first plurality of sense amplifiers senses the first row of memory cells.
(canceled)
(canceled)
(canceled)
(canceled)
A method of operation in a memory device having a plurality of banks, the method comprising:
- receiving a command that specifies a memory access to a predetermined bank of the plurality of banks;
- in response to the command that specifies the memory access, activating a first row of memory cells in the predetermined bank;
- and
- while activating the first row of memory cells in the predetermined bank, refreshing a second row of memory cells in the predetermined bank.
(canceled)
31-41. (canceled)
Dependencies are inferred from the claim text.