Process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, the resulting transistor device, an electronic device comprising such transistor devices and a processor comprising at least one such device

A fabrication process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire of the network and connected by a channel and each elementary transistor including a gate electrode surrounding each vertical nanowire of the network, the drain, source and gate electrodes of the elementary transistors implemented on the nanowires are respectively connected to each other so as to form unique drain, source and gate electrodes of the transistor device,

• wherein it comprises the following steps:
• producing source and drain electrodes at each end of each vertical nanowire, the source and drain electrodes being positioned symmetrically with respect to the gate electrode of each elementary transistor implemented on a nanowire;
• creating a gate electrode by depositing a layer of dielectric material surrounding a portion of each nanowire and depositing a layer of conductive material around each layer of dielectric material surrounding the portion of each nanowire, the layer of conductive material being unique for all of the nanowires of the network and the thickness of the layer of conductive material corresponding to the length of the gate of the transistor device;
• and
• insulating each electrode using a planar layer of a dielectric material so as to form a nanoscale gate and insulate the contacts between the source and the gate and between the drain and the gate of each elementary transistor implemented on a nanowire.

A field-effect transistor device implemented on a network of vertical nanowires including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire of the network and connected by a channel and each elementary transistor including a gate electrode surrounding each vertical nanowire of the network, the drain, source and gate electrodes of the elementary transistors implemented on the nanowires are respectively connected to each other so as to form unique drain, source and gate electrodes of the transistor device, wherein:

• the source and drain electrodes are positioned symmetrically with respect to the gate electrode of each transistor implemented on a nanowire;
• the gate electrode of a transistor is formed by a layer of dielectric material surrounding a portion of each nanowire and a layer of conductive material around each layer of dielectric material surrounding the portion of each nanowire, the layer of conductive material being unique for all of the nanowires of the network and the thickness of the layer of conductive material corresponds to the length of the gate of the transistor device;
• and
• the device includes a dielectric material so as to insulate each source and drain electrode to form the contacts between the source and gate and between the drain and gate of each transistor implemented on a nanowire.