Quasi-vertical structure for high voltage mos device

A method of fabricating a semiconductor device comprising:

• implanting a buried layer of a first dopant type on a substrate;
• forming a second layer over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer;
• implanting a first well of a second dopant type in the second layer;
• forming a gate on top of the first well and the second layer;
• implanting a first source region of the first dopant type in the first well;
• etching a trench in the second layer and/or the first well to expose a first portion of the buried layer;
• depositing an oxide in the trench;
• forming a hole in the oxide that exposes a second portion of the buried layer;
• implanting an drain region in the second portion of the buried layer;
• and
• forming a drain electrode in the hole.

A semiconductor device, comprising:

• a buried layer having a first dopant type disposed in a substrate;
• a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer;
• a first well of a second dopant type disposed in the second layer;
• a first source region of the first dopant type disposed in the first well and connected to a source contact on one side;
• a gate disposed on top of the well and the second layer;
• a metal electrode extending from the buried layer to a drain contact;
• and
• an insulation layer positioned to completely separate the metal electrode from the second layer.