A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of:
- forming a plurality of element regions and an element isolation region in a semiconductor substrate, the plurality of element regions being extended in a first direction and arranged in parallel, the element isolation region isolating the element regions from each other and being filled with a first insulating film;
- forming a plurality of memory cell gate electrodes on the element regions, the plurality of memory cell gate electrodes being extended in a second direction and arranged in parallel, the second direction being orthogonal to the first direction;
- forming two selection gate electrodes on the element regions, the two selection gate electrodes being extended in the second direction and arranged adjacent to each other in parallel;
- etching the first insulating film in such a manner that the first insulating film remains at least under the selection gate electrodes, after forming the memory cell gate electrodes and selection gate electrodes;
- forming a first resist pattern opened above a portion between the two selection gate electrodes;
- forming a second insulating film on the first resist pattern, on the selection gate electrodes, and under the selection gate electrodes in the element isolation region, the second insulating film having an etching rate in an etching solution lower than that of the first insulating film;
- performing first etching process etching the second insulating film to form a first sidewall insulating film on side surfaces of the selection gate electrodes facing each other;
- removing the first resist pattern;
- forming a third insulating film on the memory cell gate electrodes in such a manner that air gaps are formed between the memory cell gate electrodes;
- forming a second resist pattern opened above the portion between the two selection gate electrodes;
- performing second etching process using the second resist pattern as a mask to form a second sidewall insulating film on the side surfaces of the selection gate electrodes facing each other;
- removing the second resist pattern;
- forming a third resist pattern opened above the portion between the two selection gate electrodes;
- performing third etching process using the third resist pattern as a mask to remove the first sidewall insulating film and the second sidewall insulating film;
- removing the third resist pattern;
- forming a fourth insulating film serving as an etching stopper film on the element regions between the two selection gate electrodes;
- forming a fifth insulating film on the fourth insulating film, the fifth insulating film filling the portion between the two selection gate electrodes;
- forming a fourth resist pattern opened above the portion between the two selection gate electrodes;
- performing fourth etching process using the fourth resist pattern as a mask to remove the fifth insulating film with the fourth insulating film used as an etching stopper;
- and
- performing fifth etching process to remove the fourth insulating film, thereby forming a contact hole.